Boolean Minimization, Permutations, Random Numbers, Logic Design and Simulation
Design and analysis of Boolean equations and state machines is often an extremely complex and time consuming task. Even when a solution is found it can be very difficult to analyze or modify.
Simple Solver provides a suite of five design tools:
1. Boolean Equation Processor
2. Permutation Generator
3. Random Number Generator
4. Logic Simulator
5. Automatic Logic Synthesizer
These tools can be used to minimize, simplify and reduce Boolean equations and digital logic circuits.
Boolean Minimization
Reduces Boolean equations and generates truth tables for one or a series of Boolean equations. Operator formats are supported for a variety of languages including: ABEL, C, C++, PALASM, VB, Verilog and VHDL.
Permutation
Can be used for a variety of applications such as generating binary, octal, hexadecimal or decimal number tables. Includes name mapping.
Random Number
Can be used for many purposes: shuffling 52 numbers (like a deck of cards), randomly selecting a subset of operations for sample testing, and so forth.
Logic Simulation
Tests circuit functionality and timing problems such as flip-flop setup and hold times, race conditions and glitches/spikes.
Logic Synthesis
Performs automatic
design and simulation of digital logic
circuits from
truth table or waveform inputs. All circuit types and
configurations are supported: Combinational, Sequential,
Synchronous and Asynchronous.
Automated design is done by searching for circuits that match the
transfer function of the input - output signals. In general,
the first circuit found will be the simplest possible
solution.