Simple Solver - Boolean

Boolean Equation Processor

The Boolean EQuation (BEQ) Processor inverts, minimizes and generates truth tables for one or more Boolean equations.

Screenshot

If one or more Input Equations are selected (highlighted), only the selected equation(s) will be processed. Otherwise all equations will be processed.

1. Boolean Equation Format

Each equation must consist of one symbol name on the left-hand side of the "=" sign, an "=" or ":=", and one or more symbol names on the right-hand side of the "=" sign.

Left-Hand side of equation
Each equation must start with "name :=" or "name =".
Optionally the name can be preceded by a NOT operator to invert the polarity of the name.

Right-Hand side of equation
The right-hand side contains a Boolean expression of symbol names, operators and optional pairs of parentheses.
Each equation must end with a semi-colon (;). Examples: F = A or (B and C); not F = !(A or (B and C));

2. Boolean Operators

Any of the following symbols can be used in the Input Equations.

NOT: 
not   /  !

AND:  and   *  & 
&&

OR:   or    + 
#  ||

NAND: nand

NOR:  nor

XOR:  xor   $  ^

XNOR: xnor

Example: X = !(A&&B && C) || (D && E);

Operator precedence (order of evaluation) is

1. Not
2. And/Nand
3. Or/Nor/Xor/Xnor

If the same operator is used multiple times, the operators are evaluated from left to right.
Parentheses can be used to explicitly override the order of precedence.

3. Symbol Names

Any character can be used in a Symbol name except: space tab * + & | = # ( ) $ ^ / ! : ; or character(s) beginning a comment.

4. Case

Symbol names are case sensitive, Operators (and/OR/nOt) are not.

5. Comments

Comments begin with "//" or "--" or "'" and extend to the end of the line.

6. Limits

10 Symbol names, 32 characters/name.

7. Output Options

Minimize - Each Input Equation is minimized

Invert & Minimize - Each Input Equation is inverted and then minimized

Truth Table - A truth table is generated for each Input Equation

Sort Names - Symbol names in each minterm and the Truth Table are sorted in alphabetical order

Show Only Last - Only results of the last selected option (such as Truth Table) are shown in the Output text box

Operator Format - Selects the format of Boolean NOT AND OR operators shown in the Output window

Format   NOT    AND     OR      Notes
0      not    and     or      VHDL VB
1       /      *      +       PALASM
2       !      &      #       ABEL
3       !      &&     ||      C C++ Verilog

4 SYN Format

Format "4" generates a specially formatted Output for export to the Synthesis function.
Currently this is done by Copy (Ctrl C) from the Boolean Output window and Paste (Ctrl V) to the Synthesis Input window.

The Synthesis function can then:

Reformat the Boolean truth table as a waveform or timing diagram (SYN Timing Only option)
Find the minimal Boolean equation using any mix of part types (and, or, inv, nand, nor, xor, xnor)
Generate one or more corresponding logic circuits