Simple Solver

Boolean Minimization, Permutations, Random Numbers, Logic Design and Simulation

Minimizer Algorithms

Boolean Minimization uses a Karnaugh map approach, also known as a Veitch diagram, K-map, or KV-map.
The Boolean Equation software follows the Quine-McCluskey algorithm to implement Karnaugh mapping.

In contrast, Logic Synthesis performs automated logic synthesis by searching for circuits that provide the transfer function specified by the input and output signal waveforms.
Because the search begins with the fewest possible gates or flip flops, the first circuit solution found will generally be the simplest possible solution.

The below table compares the minimization algorithms of the two tools:


Boolean vs. Synthesis Minimization

beq vs syn

Boolean Minimization

BEQ reduces Boolean equations and generates truth tables for one or a series of Boolean equations. Operator formats are supported for a variety of languages including: ABEL, C, C++, PALASM, VB, Verilog and VHDL.

Synthesis Minimization

SYN performs automatic design by searching for circuits that match the transfer function of the input - output signals. In general, the first circuit found will be the simplest possible solution.