Logic Synthesis
The Synthesis function (SYN) provides automatic design and simulation of digital logic functions.
There are two modes of
operation -
Hardware (HW) and Software (SW). While both modes perform
functional simulations of candidate circuits, the HW mode performs
additional timing checks including flip-flop setup/hold times, race
conditions and spike/glitch detection which are generally not
applicable to software solutions.
Output formats include Boolean equations, gate-level logic schematics,
truth tables and timing diagrams.
Screenshot
All logic types and configurations are supported:
Combinational
Sequential
Synchronous
Asynchronous
Automatic Design - SYN searches for one or more digital circuits that provide the transfer function specified by the input/output signal timing diagrams or waveforms. In general, the first circuit solution found will be the simplest solution possible. Refer to US Patent 6253365.
Because of this, SYN provides both automated design and minimization. For example, if the truth table of a Boolean equation is specified as an input to SYN, the first solution found will be the minimal form of the Boolean equation.
Simulation - Simulates each logic circuit and displays its functional operation including the effects of glitches and flip-flop setup/hold violations.
Design & Simulation features
- 10 part types including and, or, nand, nor, xor, xnor logic gates and D flip-flops- 2 to 8 inputs per logic gate
- flip-flop state initialization
- optional spike/glitch filters
- 5 logic states - 0 1 x r f
- clock/data signal types
GETTING STARTED - The following text is an extract from the SYN Help file:
The Input Specification window contains the Design Specification for the logic or state machine. Data can be entered manually or from a file (File/Open or Examples menus).Example
The following example is from file "2-input AND Default.txt" which can be loaded using the SYN Examples menu:
A 0101; 'input #1
B 0011; 'input #2
C 0001; 'output
A and B are inputs, C is the output. C is specified as the logical 'AND' of A and B.
Circuit synthesis is started by clicking the "Go" button.
The circuit found is shown in the Output Circuits / Timing window if the Logic Circuit option is checked.
Similarly, the corresponding Boolean equation is displayed in the Output Circuits / Timing window if the Boolean Eqn option is checked.
The truth table or waveform of the circuit is also shown with several possible format options.
Other Examples
The files in the Examples\Synthesis directory demonstrate the flexibility of SYN as well as usage of its Advanced Options.
For example:
"DFF Edge-Triggered.txt" synthesizes an edge-triggered D-flip-flip using Nand gates.
"Serial Input 32-bit.txt" illustrates a relatively complex sequential circuit specification.
ADVANCED FEATURES and OPTIONS
Detailed instructions for the advanced features are provided in the SYN Help file.